`include "../../src/registers.v"

`timescale 1ps/1ps
module testbench;

    reg[4:0] readRegister1, readRegister2, writeRegister; //要读/写的寄存器
    initial readRegister1 = 5'b00000;
    initial readRegister2 = 5'b00000;
    initial writeRegister = 5'b00000;

    reg regWrite; //寄存器写信号
    initial regWrite = 0;

    reg[31:0] writeData;  //写寄存器数据
    initial writeData = 32'h0000;

    reg clk, reset;
    initial clk = 1;
    initial reset = 0;

    wire[31:0] readData1, readData2; //读寄存器数据

    always #5 clk = ~clk;

    registers U0(clk, reset, readRegister1, readRegister2, writeRegister, writeData,
                    readData1, readData2, regWrite);
    initial
    begin
        reset = 1;

        #10
        readRegister1 = 5'b00001;
        readRegister2 = 5'b00010;
        regWrite = 0;

        #10
        regWrite = 1;
        writeRegister = 5'b00001;
        writeData = 32'h1234;

        #10
        regWrite = 1;
        writeRegister = 5'b00010;
        writeData = 32'h2345;

        #10 
        readRegister1 = 5'b00001;
        readRegister2 = 5'b00010;
        regWrite = 0;

        #10
        $stop;
    end
    
    initial
    begin
        $dumpfile("registers.lxt");
        $dumpvars;
    end
endmodule